Samir Palnitkar - Verilog HDL: A Guide to Digital Design and Synthesis [With CDROM]

Verilog allows signals to have logic values and strength values. Logic values are , , x , and z . Logic strength values are used to resolve combinations of multiple signals and to represent behavior of actual hardware elements as accurately as possible. Several logic strengths are available. shows the strength levels for signals. Driving strengths are used for signal values that are driven on a net. Storage strengths are used to model charge storage in trireg type nets, which are discussed later in this appendix.

Logic strength values can be used to resolve signal contention on nets that have multiple drivers.There are many rules applicable to resolution of contention. However, two cases of interest that are most commonly used are described below.

If two signals with same known value and different strength drive the same net, the signal with the higher strength wins.

In the example shown, supply strength is greater than pull . Hence, Su1 wins.

When two signals with opposite value and same strength combine, the resulting value is x .

We discussed resolution of signal contention by using strength levels. There are other methods to resolve contention without using strength levels. Verilog provides advanced net declarations to model logic contention.

The keywords wire and tri have identical syntax and function. However, separate names are provided to indicate the purpose of the net. Keyword wire denotes nets with single drivers, and tri is denotes nets that have multiple drivers. A multiplexer, as defined below, uses the tri declaration.

module mux(out, a, b, control);output out;input a, b, control;tri out;wire a, b, control;bufif0 b1(out, a, control); //drives a when control = 0; z otherwisebufif1 b2(out, b, control); //drives b when control = 1; z otherwiseendmodule

The net is driven by b1 and b2 in a complementary manner. When b1 drives a, b2 is tristated; when b2 drives b, b1 is tristated. Thus, there is no logic contention. If there is contention on a tri net, it is resolved by using strength levels. If there are two signals of opposite values and same strength, the resulting value of the tri net is x .

Keyword trireg is used to model nets having capacitance that stores values. The default strength for trireg nets is medium . Nets of type trireg are in one of two states:

• Driven state At least one driver drives a , , or x value on the net. The value is continuously stored in the trireg net. It takes the strength of the driver.

• Capacitive state All drivers on the net have high impedance ( z) value. The net holds the last driven value. The strength is small , medium , or large (default is medium ).

trireg (large) out;wire a, control;bufif1 (out, a, control); // net out gets value of a when control = 1; //when control = 0, out retains last value of a //instead of going to z . strength is large.

Keywords tri0 and tri1 are used to model resistive pulldown and pullup devices. A tri0 net has a value if nothing is driving the net. Similarly, tri1 net has a value if nothing is driving the net. The default strength is pull .

tri0 out;wire a, control;bufif1 (out, a, control); //net out gets the value of a when control = 1; //when control = 0, out gets the value 0 instead //of z . If out were declared as tri1 , the //default value of out would be instead of .

Keyword supply1 is used to model a power supply. Keyword supply0 is used to model ground. Nets declared as supply1 or supply0 have constant logic value and a strength level supply (strongest strength level).

supply1 vcc; //all nets connected to vcc are connected to power supplysupply0 gnd; //all nets connected to gnd are connected to ground

When there is logic contention, if we simply use a tri net, we will get an x . This could be indicative of a design problem. However, sometimes the designer needs to resolve the final logic value when there are multiple drivers on the net, without using strength levels. Keywords wor , wand , trior , and triand are used to resolve such conflicts. Net wand perform the and operation on multiple driver logic values. If any value is , the value of the net wand is . Net wor performs the or operation on multiple driver values. If any value is , the net wor is . Nets triand and trior have the same syntax and function as the nets wor and wand . The example below explains the function.

wand out1;wor out2;buf (out1, 1'b0);buf (out1, 1'b1); //out1 is a wand net; gets the final value 1'b0buf (out2, 1'b0);buf (out2, 1'b1); //out2 is a wor net; gets the final value 1'b1

A list of PLI acc_ and tf_ routines is provided. VPI routines are not listed. Names, the argument list, and a brief description of the routine are shown for each PLI routine. For details regarding the use of each PLI routine, refer to the IEEE Standard Verilog Hardware Description Language document.

[1] See the "IEEE Standard Verilog Hardware Description Language" document for details on VPI routines.

Conventions to be used for arguments are shown below.

Access routines are classified into five categories: handle, next, value change link, fetch, and modify routines.

Handle routines return handles to objects in the design. The names of handle routines always starts with the prefix acc_handle_ . See .