Mrozek - Multi-run Memory Tests for Pattern Sensitive Faults

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Semiconductor memory is a crucial part of todays electronic systems. The percentage of silicon areas devoted to memory components in embedded systems and systems-on-chip (SoCs) is still on the rise. Modern computers typically contain a variety of embedded memory arrays like caches , branch prediction tables , or priority queues for instruction execution and a main computer memory, called random access memory (RAM ). Fault-free memory operations are crucial for the correct behavior of the complete embedded system. Therefore, memory has to satisfy very high-quality constraints, ranging from 50 failing parts per million (ppm) for computer systems to less than 10 ppm for mission-critical applications. Moreover, memory chips are very often designed to exploit the technologys limits (to get the highest storage density and access speed), which makes them prone to defects. Hence, efficient techniques for production testing as well as for periodic maintenance testing are mandatory to guarantee the required quality standards. However, advances in memory technology and system design have turned memory testing into not a trivial task. The complexity of the memory chips makes fault modeling and testing a more and more challenging problem. As a result, testing semiconductor memories is becoming a major cost factor in the production of memory chips for modern computers. Therefore, the selection of the most appropriate diagnostic techniques, test algorithms, and target set of fault models is still a very hot topic in both academia and the industry.

Memory faults can be divided on the basis of the number of memory cells being faulty, namely into one-cell faults (e.g., stuck-at faults , stuck open faults , and transition faults ), and multiple cells faults (e.g., coupling idempotent faults , coupling inversion faults, and pattern sensitive faults ( PSF )) . The first group of faults is well detectable by existing classical tests . In the case of the second group of faults, the problem is much more difficult. Although many approaches have been proposed in the literature, the issue of efficient detection of multiple cell faults is still open. Moreover, memory capacity and density are still on the rise. This is the reason why one of the main failure mechanisms that makes memory testing challenging is very susceptible to interactions between adjacent cells. Neighborhood pattern sensitive fault ( NPSF ) is a classical fault model that covers such interactions. However, the classical NPSF model is not always a good solution because of scrambling . In addition, the scrambling information is not always available. It may not be published by the memory manufacturers or it can undergo changes. That is why an unrestricted pattern sensitive fault ( PSF k ) model, where k denotes the number of any arbitrary memory cells out of the N -cells memory involved in the particular fault, one of which is a base cell , while k 1 cells are the neighborhood cells , as have been shown in various researches, is more suitable for the case of complex memory fault modeling.

Due to the linear complexity, regularity, symmetry, and simplicity of the hardware implementation, the march tests are usually a preferred and often the only reasonable method for RAM testing. The conventional march memory tests have high fault coverage , especially for simple faults like stuck-at, transition, or coupling faults. At the same time standard march tests, which are based on only one run of the test, are becoming insufficient for complex faults like PSF k .

To increase fault coverage, the multi-run testing technique can be used. The idea of multi-run tests was originally formulated in the context of transparent testing, , and later exhaustive and pseudo-exhaustive RAM testing. According to this idea, the same testing procedure is executed several times, each time with different initial conditions. To cover a wide range of memory faults (including PSF k ), the test process requires multiple runs of one or more memory tests. It is obvious that the fault coverage of such testing processes depends both on the test used (including number of its iterations) and initial conditions (including memory backgrounds and address sequences).

The principal emphasis of this study is directed at the efficient cover of complex faults by multi-run transparent march tests . This is the first book that exclusively covers this problem. To accomplish the main goal, the backgrounds selection as well as address reordering algorithms in the multi-run transparent march testing process are analyzed and thoroughly investigated. As a result, formal methods for multi-run test generation and many solutions to increase their efficiency are proposed. All presented ideas are deeply analyzed by means of both analytical investigations and numerical simulations.

Chapters presents an introduction to deterministic functional RAM testing. The memory chip model is given, and a set of traditional functional fault models as well as basic march tests are discussed.

Chapter focuses on pattern sensitive faults. First, neighborhood pattern sensitive faults and classical algorithms for their detection are analyzed. Then, the unrestricted pattern sensitive faults and their detection capabilities by march tests are investigated . After that, the limitation of march tests in terms of the pattern sensitive fault detection process is presented. Finally, it is pointed out that one of the constructive solutions to achieve high fault coverage in terms of pattern sensitive faults is multi-run testing. This is the main object of interest for further studies; thus, the introduction to multi-run tests is given in the last section of this chapter.