Zaks Rodnay - Microprocessor Interfacing Techniques (3rd ed.)

Zaks, Rodnay

Lesea, Austin

This book was produced in EPUB format by the Internet Archive.

The book pages were scanned and converted to EPUB format automatically. This process relies on optical character recognition, and is somewhat susceptible to errors. The book may not offer the correct reading sequence, and there may be weird characters, non-words, and incorrect guesses at structure. Some page numbers and headers or footers may remain from the scanned page. The process which identifies images might have found stray marks on the page which are not actually images from the book. The hidden page numbering which may be available to your ereader corresponds to the numbered pages in the print edition, but is not an exact match; page numbers will increment at the same rate as the corresponding print edition, but we may have started numbering before the print book's visible page numbers. The Internet Archive is working to improve the scanning process and resulting books, but in the meantime, we hope that this book will be useful to you.

The Internet Archive was founded in 1996 to build an Internet library and to promote universal access to all knowledge. The Archive's purposes include offering permanent access for researchers, historians, scholars, people with disabilities, and the general public to historical collections that exist in digital format. The Internet Archive includes texts, audio, moving images, and software as well as archived web pages, and provides specialized services for information access for the blind and other persons with disabilities.

Created with abbyy2epub (v.1.7.2)

INTERFACING

TECHNIQUES

MICROPROCESSOR

INTERFACING

TECHNIQUES

RODNAYZAKS AUSTIN LESEA

THIRD EDITION

SYBEX

SAN FRANCISCO PARIS DUSSELDORF LONDON

SYBEX is a registered trademark of SYBEX, Inc.

SYBEX is not affiliated with any manufacturer.

Every effort has been made to supply complete and accurate information. However, SYBEX assumes no responsibility for its use, nor for any infringements of patents or other rights of third parties which would result.

Copyright1977,1978,1979, SYBEX Inc., 2021 Challenger Drive #100, Alameda, CA 94501. World rights reserved. No part of this publication may be stored in a retrieval system, transmitted, or reproduced in any way, including but not limited to photocopy, photograph, magnetic or other record, without the prior agreement and written permission of the publisher.

Library of Congress Card Number: 78-55237 ISBN 0-89588-029-6

Manufactured in the United States of America

20 19 18 17 16 15 14 13 12

ACKNOWLEDGEMENTS

The following persons or companies have supplied valuable information, photographs, programs or schematics of their products or projects: Although not all information supplied could be used, their cooperation is gratefully acknowledged.

Intel, Motorola, Persci (disks), Shugart (disks), Thomson-CSF (CRTC board), David Reinagel (Music Synthesis), Rockwell, Data I/O (programmer), Prolog (programmer), Zilog, Hewlett-Packard (analyzers), Control Data (disks), North Star, Imsai, Altair (S100 bus), Tarbell (cassette interface), Component Sales (keyboards), MOS Technology, Advanced Micro Devices, Fairchild, NEC, Western Digital, Dynabyte (RAM), National Semiconductor, Analog Devices, Lawrence Laboratory, University of California at Berkeley, Power-One (power supply), Fluke, Biomation (analyzer), Trendar (fault analysis)

ALSO AVAILABLE IN:

-FRENCH

- GERMAN

- DUTCH

- SWEDISH

- JAPANESE

- ITALIAN

(more to be published)

TABLE OF CONTENTS

PREFACE 3

I. INTRODUCTION 15

Concepts, Techniques to be discussed, Bus Introduction, Bus Details

II. ASSEMBLING THE CENTRAL PROCESSING UNIT .... 25

Introduction, The 8080, The 6800, The Z-80: Dynamic Memory, The 8085

III. BASIC INPUT-OUTPUT 56

Parallel, Serial LSI Interface Chips for 8080, 6800 Systems, Interrupts, DMA Controllers, Useful Circuits

IV. INTERFACING THE PERIPHERALS 100

Keyboard, LED, Teletypewriter, Paper Tape Reader, Stepper Motors, Credit Card Reader, CRT, Intelligent Interfacing, Cassette Tape Recorder, Floppy-Disk, Dynamic Memories Revisited, Music Synthesizer

V. ANALOG CIRCUITRY - A/D and D/A CONVERSION .. 260

Introduction, Conceptual D/A, Practical D/A, Real Products, The A/D, Sampling Theorem, Successive Approximation, Integration, Direct Comparison Conversion, Real Products, Interfacing D/As, Interfacing A/Ds, A Data Collection Sub-system, Scaling, Offset, Conclusion

VI. BUS STANDARDS 322

Parallel: SI00, 6800, IEEE-488, An IEEE-488 Interface Example, CAMAC. Serial: EIA-RS232C, RS422, RS423, Synchronous Formats, An SI00 Interface Example

Vn. CASE-STUDY: A 32-CHANNEL MULTIPLEXER 377

Introduction, Specifications, Architecture, Software, CPU Module, RAM Module, US ART Module, Host Interface Module, Conclusion

VIII. DIGITAL TROUBLE-SHOOTING 399

Introduction, What Goes Wrong: Components, Noise, Software; The Tools and Methods: VOM, D VM, Oscilloscope, Logic Probes, Signature Analysis, Emulation, Simulation, Logic State Analyzers, Case-Study Trouble History, The Perfect Bench

IX. CONCLUSION - EVOLUTION 436

The New Chips: 1-Chip Systems, Plastic Software, The Universal Programmable Interface

APPENDIX A 439

Manufacturers.

APPENDIX B 441

SI 00 Manufacturers

APPENDIX C 447

Conversion Table Decimal, Binary, Hex, Octal

APPENDIX D 448

RS232C Signals

APPENDIX E 449

IEEE-488 Signals

APPENDIX F 450

Acronyms

INDEX 453

LIST OF ILLUSTRATIONS

1-1 Standard Microprocessor System 18

1-2 Signal Equivalences 20

1-3 8080 Control Signals 22

1-4 Basic 8080 Instruction Cycle 22

1-5 DBIN Timing 23

1-6 6800 Bus Signals 23

1- 7 6800 Bus Control Detail 24

2- 0 Z-80 CPU Board 25

2-1 Devices Integrated Versus Time 27

2-2 Yield versus Die Size 27

2-3 Typical System Architecture 29

2-4 Linear Selection 30

2-5 Fully Decoded Selection 31

2-6 8205 Decoder 32

2-7 Intel Dynamic RAMs 33

2-8 Buffering Address and Control Lines 34

2-9 Buffering the Data Bus 35

2-10 8080 Completed CPU 36

2-11 8224 Schematic 36

2-12 System Controller Using 8212 and 8216s 37

2-13 8228 System Controller 38

2-14 2708 Selection Using 8205 39

2-15 PROM Timing , 39

2-16 Buffering RAM Data Lines Using Bus Transceiver 40

2-17 Connecting the 2111 RAM 41

2-18 RAM Timing 42

2-19 Complete 8080 System Memory 43

2-20 6800 System Block Diagram 44

2-21 6800 Non-Overlapping Clock Signals 44

2-22 Buffering 6800 Buses - Suggested Devices 45

2-24 Chip selection Allowing 16 Device Connection 46

2-23 6800 Control Signals 46

2-24 4-Chip Selection Allowing 16-Device Connection 46