Smith David. - Virtual Parallel Lines (Journal of Ideas and Inventions - Special Editions Book 1)

Introduction

Time-division multiple-access (TDMA) and frequency-division multiple-access (FDMA) are two main principles of multiple-access on which data communication systems have been built. TDMA provides a means by which a number of stations may gain access to the same channel link by the use of time-domain multiplexing, where each user is allocated a length of time for transmission of data down the channel. An example of this would be in the multiple channel arrangement of B-ISDN.

FDMA allows multiple stations to transmit data along the same channel medium at the same time, but in different frequency bands, referred to as Frequency Domain Multiplexing (FDM). Non-division multiple-access (NDMA) is a further principle of multiple-access in which a number of stations can each transmit their bit-streams, over the same channel medium, at the same time and at the same frequency.

The principle of NDMA is based on Virtual Parallel Lines (VPL) which would carry data from independent sources, simultaneously, over a single transmission medium. VPL is outlined in the present text, with applications in computer networks and data communications, and implications in the design of digital bus-based systems.

Digital Integrated Circuits (ICs) require an increasing number of data and address lines - from 8-bit and 16-bit microcontrollers to 16-bit and 32-bit CPUs, and 64-bit CPUs utilised in high performance computers and servers. This increasing pin count leads directly to an increasing external packaging area.

Two of the current packaging methods used to overcome the increasing demand on printed circuit board (PCB) area are chip-scale packaging and serial bus devices. Chip-scale packaging is outlined by J. Fjelstad [8].

This method aims to place all, or most, of the pins on the underside of the package, directly beneath the chip, thus reducing the amount of spread required on the PCB. Hence, Fjelstad also refers to it as 'Chip-size' packaging. With this method Philips Semiconductors has been able to define the BGA596, which is a plastic ball grid array package (type SOT586-1) with 596 solder balls covering 66% of the underside surface.

Serial bus chips provide a single input/output pin for data storage or other functions. The Dallas Semiconductor DS2506 is a 64k-bit EPROM using serial bus technology. It is housed in a 3-pin PR35 package, similar type and size to the TO-92 packaging used for the BC182L discrete bipolar transistor. Compare this to the Advanced Micro Devices AM27C64-90, a 64k-bit EPROM with parallel data access, in a 28-pin ceramic DIL package.

A third type of package reduction for digital ICs could reduce the mounting area on circuit boards. The data and address buses could each be replaced by a single VPL track, thus reducing the pin count by

b-v

where b is the total number of data and address bus lines to be replaced and v is the total number of VPL tracks replacing the bus tracks. All of these pins on the outside of the packaging are removed, except for the two VPL pins for the two buses.

If there were 16 data lines in a digital bus-based circuit board, then a single VPL path would provide fewer copper tracks. The scale of reduction would be

((b-v)/b) x 100%

And for a 16-bit data bus

(15/16) x 100% = 93.75% reduction

This could mean a 93.75% reduction in the area of a single-layer PCB. However, this reduction in area will be fully appreciated in a PCB that is heavily populated with parallel bus tracks.

Note that this amount of reduction in board area would be challenged by the necessary width of the VPL lines, required to carry the VPL encoded (analogue) signal. Therefore, the reduction in board area could be less than 93.75%.

If the bus tracks are distributed throughout several layers in the PCB, then the overall board reduction will be diluted by the number of layers

((b-v)/(bL)) x 100%

where L is the number of layers in the circuit board.

A further reduction in board space can be achieved by mounting the VPL IC package on one edge, as single-in-line (SIL) packages.

Figure 4.1 shows the components of a VPL bus-based network segment. Five stations are shown connected to the segment, along with a VPL router, to which is attached four servers for file sharing, printing, email and an Internet connection.

Each station houses a VPL interface card (VIP). A parallel attachment unit (PAU) is inserted between each length of VPL cable. The parallel attachment cable (PAC) is the drop cable required between the VPL Interface Card (VIC) and PAU to connect the station to the VPL cable. An internal schematic of the PAU is shown in figure 4.2.

Five independent data channels run from the VPL decoder to the encoder. The PAC is shown connected in the PAU. Five pairs of data paths run to the VIC housed in the connected station. The VIC and the network driver and management software would determine the channel allocated to that station.

Figure 4.3 shows a VPL router in which the signal on the VPL cable is decoded and encoded for bi-directional data flow. The switching unit simultaneously connects the stations to servers, to other networks or to another station on the same VPL segment.

For VPL hardware, investigate issues in LLC protocol specification (IEEE 802.2). Define primitive parameters and MAC addressing. [Refs. 4,9]

For VPL hardware, investigate issues in MAC protocol specification. Define primitive parameters, circuits and signals. [Refs. 4,9]

Aim to produce working prototypes of the components of a VPL network, such as VPL interface card, parallel attachment cable, parallel attachment unit, VPL network cable, router, hub and VPL encoder and decoder.

The loss of signal strength over a length of VPL cable.

Consider

10 log (Pout/Pin)

[Ref. 1]

Instantaneous voltage,

a = A sin( ft + )

where A is the maximum amplitude, f is the carrier frequency, tis time an d is the phase.

The types of modulation to consider are:

Frequency Shift Keying (FSK)

Phase Shift Keying (PSK)

Amplitude Shift Keying (ASK)

In particular, the encoding techniques and specifications of modems and Local Area Networks (LANs) will be considered. [Ref. 1]

C = B log (1+s/n) bits per second

For modem encoding, the channel capacity is increased when the number of bits per cycle is increased. For example, the Dibit encoding technique uses one of four phases of the carrier signal to represent one of the four states of a 2-bit binary code. This is also known as Quadrature Phase Shift Keying (QPSK).