Pyeatt Larry D - ARM 64-Bit Assembly Language
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- Book:ARM 64-Bit Assembly Language
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- Year:2019;2020
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First edition
Larry D. Pyeatt
William Ughetta
Newnes is an imprint of Elsevier
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Notices
Knowledge and best practice in this field are constantly changing. As new research and experience broaden our understanding, changes in research methods, professional practices, or medical treatment may become necessary.
Practitioners and researchers must always rely on their own experience and knowledge in evaluating and using any information, methods, compounds, or experiments described herein. In using such information or methods they should be mindful of their own safety and the safety of others, including parties for whom they have a professional responsibility.
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Library of Congress Cataloging-in-Publication Data
A catalog record for this book is available from the Library of Congress
British Library Cataloguing-in-Publication Data
A catalogue record for this book is available from the British Library
ISBN: 978-0-12-819221-4
For information on all Newnes publications visit our website at https://www.elsevier.com/books-and-journals
Publisher: Mara Conner
Acquisition Editor: Tim Pitts
Editorial Project Manager: Joshua Mearns
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Typeset by VTeX
- Table 1.1 Values represented by two bits.
- Table 1.2 The first 21 integers (starting with 0) in various bases.
- Table 1.3 The ASCII control characters.
- Table 1.4 The ASCII printable characters.
- Table 1.5 Binary equivalents for each character in Hello World.
- Table 1.6 Binary, hexadecimal, and decimal equivalents for each character in Hello World.
- Table 1.7 Interpreting a hexadecimal string as ASCII.
- Table 1.8 Variations of the ISO 8859 standard.
- Table 1.9 UTF-8 encoding of the ISO/IEC 10646 code points.
- Table 3.1 Flag bits in
. - Table 3.2 AArch64 condition modifiers.
- Table 3.3 Summary of valid immediate values.
- Table 3.4 Load/Store memory addressing modes.
- Table 4.1 Formats for Operand2.
- Table 4.2 Shift and rotate operations in Operand2.
- Table 4.3 Extension operations in Operand2.
- Table 7.1 Performance of
implementations on an nVidia Jetson TX-1. - Table 8.1 Natural and truncated formats for the powers of x needed by the Taylor series.
- Table 8.2 Reciprocals for the terms two through nine of the Taylor series.
- Table 8.3 Formats for the powers of x and the constant reciprocals for the first nine terms of the Taylor series.
- Table 8.4 Performance of sine function with various implementations.
- Table 8.5 Format for IEEE 754 Half-Precision.
- Table 9.1 Condition code meanings for ARM and FP/NEON.
- Table 9.2 Performance of sine function with various implementations.
- Table 10.1 Performance of sine function with various implementations.
- Table 11.1 Raspberry Pi GPIO register map.
- Table 11.2 GPIO pin function select bits.
- Table 11.3 GPPUD control codes.
- Table 11.4 Raspberry Pi expansion header useful alternate functions.
- Table 11.5 Raspberry Pi PWM register map.
- Table 11.6 Raspberry Pi PWM control register bits.
- Table 11.7 Clock sources available for the clocks provided by the clock manager.
- Table 11.8 Some registers in the clock manager device.
- Table 11.9 Bit fields in the clock manager control registers.
- Table 11.10 Bit fields in the clock manager divisor registers.
- Table 11.11 Raspberry Pi UART0 register map.
- Table 11.12 Raspberry Pi UART data register.
- Table 11.13 Raspberry Pi UART Receive Status Register/Error Clear Register.
- Table 11.14 Raspberry Pi UART Flags Register bits.
- Table 11.15 Raspberry Pi UART integer baud rate divisor.
- Table 11.16 Raspberry Pi UART fractional baud rate divisor.
- Table 11.17 Raspberry Pi UART line control register bits.
- Table 11.18 Raspberry Pi UART Control Register bits.
- Table 12.1 The ARM User and System Registers.
- Table 12.2 Mode bits in the PSTATE register.
- Fig. 1.1 Simplified representation of a computer system.
- Fig. 1.2 Stages of a typical compilation sequence.
- Fig. 1.3 Tables used for converting between binary, octal, and hexadecimal.
- Fig. 1.4 Four different representations for binary integers.
- Fig. 1.5 Complement tables for base ten and base two.
- Fig. 1.6 A section of memory can be viewed in different ways.
- Fig. 1.7 Typical memory layout for a program with a 32-bit address space.
- Fig. 2.1 Equivalent static variable declarations in Assembly and C.
- Fig. 3.1 A simplified view of the AArch64 architecture.
- Fig. 3.2 AArch64 general purpose registers () and special registers.
- Fig. 3.3 Fields in the PSTATE register.
- Fig. 5.1 AArch64 User Program Registers.
- Fig. 6.1 Binary tree of word frequencies.
- Fig. 6.2 Binary tree of word frequencies with index added.
- Fig. 6.3 Binary tree of word frequencies with sorted index.
- Fig. 7.1 In signed 8-bit math, 110110012 is 3910
. - Fig. 7.2 In unsigned 8-bit math, 110110012 is 21710.
- Fig. 7.3 Multiplication of large numbers.
- Fig. 7.4 Longhand division in decimal and binary.
- Fig. 7.5 Flowchart for binary division.
- Fig. 8.1 Examples of fixed point signed arithmetic.
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