Hao Yu - ReRAM-based Machine Learning (Computing and Networks)
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The transition towards exascale computing has resulted in major transformations in computing paradigms. The need to analyze and respond to such large amounts of data sets has led to the adoption of machine learning (ML) and deep learning (DL) methods in a wide range of applications.
One of the major challenges is the fetching of data from computing memory and writing it back without experiencing a memory-wall bottleneck. To address such concerns, in-memory computing (IMC) and supporting frameworks have been introduced. In-memory computing methods have ultra-low power and high-density embedded storage. Resistive Random-Access Memory (ReRAM) technology seems the most promising IMC solution due to its minimized leakage power, reduced power consumption and smaller hardware footprint, as well as its compatibility with CMOS technology, which is widely used in industry.
In this book, the authors introduce ReRAM techniques for performing distributed computing using IMC accelerators, present ReRAM-based IMC architectures that can perform computations of ML and data-intensive applications, as well as strategies to map ML designs onto hardware accelerators.
The book serves as a bridge between researchers in the computing domain (algorithm designers for ML and DL) and computing hardware designers.
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IET COMPUTING SERIES 39
ReRAM-based Machine Learning
Other volumes in this series:
| Volume 1 | Knowledge Discovery and Data Mining M.A. Bramer (Editor) |
| Volume 3 | Troubled IT Projects: Prevention and turnaround J.M. Smith |
| Volume 4 | UML for Systems Engineering: Watching the wheels, 2nd Edition J. Holt |
| Volume 5 | Intelligent Distributed Video Surveillance Systems S.A. Velastin and P. Remagnino (Editors) |
| Volume 6 | Trusted Computing C. Mitchell (Editor) |
| Volume 7 | SysML for Systems Engineering J. Holt and S. Perry |
| Volume 8 | Modelling Enterprise Architectures J. Holt and S. Perry |
| Volume 9 | Model-based Requirements Engineering J. Holt, S. Perry and M. Bownsword |
| Volume 13 | Trusted Platform Modules: Why, when and how to use them Ariel Segall |
| Volume 14 | Foundations for Model-based Systems Engineering: From patterns to models J. Holt, S. Perry and M. Bownsword |
| Volume 15 | Big Data and Software Defined Networks J. Taheri (Editor) |
| Volume 18 | Modeling and Simulation of Complex Communication M.A. Niazi (Editor) |
| Volume 20 | SysML for Systems Engineering: A Model-based approach, 3rd Edition J. Holt and S. Perry |
| Volume 23 | Data as Infrastructure for Smart Cities L. Suzuki and A. Finkelstein |
| Volume 24 | Ultrascale Computing Systems J. Carretero, E. Jeannot and A. Zomaya |
| Volume 25 | Big Data-enabled Internet of Things M. Khan, S. Khan and A. Zomaya (Editors) |
| Volume 26 | Handbook of Mathematical Models for Languages and Computation A. Meduna, P. Horek and M. Tomko |
| Volume 29 | Blockchains for Network Security: Principles, technologies and applications H. Huang, L. Wang, Y. Wu and K.R. Choo (Editors) |
| Volume 32 | Network Classification for Traffic Management: Anomaly detection, feature selection, clustering and classification Zahir Tari, Adil Fahad, Abdulmohsen Almalawi and Xun Yi |
| Volume 33 | Edge Computing: Models, technologies and applications J. Taheri and S. Deng (Editors) |
| Volume 34 | AI for Emerging Verticals: Human-robot computing, sensing and networking M.Z. Shakir and N. Ramzan (Editors) |
| Volume 35 | Big Data Recommender Systems Volumes 1 and 2 Osman Khalid, Samee U. Khan and Albert Y. Zomaya (Editors) |
| Volume 40 | E-learning Methodologies: Fundamentals, technologies and applications M. Goyal, R. Krishnamurthi and D. Yadav (Editors) |
Edited by
Hao Yu, Leibin Ni and Sai Manoj Pudukotai Dinakarrao
The Institution of Engineering and Technology
Published by The Institution of Engineering and Technology, London, United Kingdom
The Institution of Engineering and Technology is registered as a Charity in England & Wales (no. 211014) and Scotland (no. SC038698).
The Institution of Engineering and Technology 2021
First published 2021
This publication is copyright under the Berne Convention and the Universal Copyright Convention. All rights reserved. Apart from any fair dealing for the purposes of research or private study, or criticism or review, as permitted under the Copyright, Designs and Patents Act 1988, this publication may be reproduced, stored or transmitted, in any form or by any means, only with the prior permission in writing of the publishers, or in the case of reprographic reproduction in accordance with the terms of licences issued by the Copyright Licensing Agency. Enquiries concerning reproduction outside those terms should be sent to the publisher at the undermentioned address:
The Institution of Engineering and Technology
Michael Faraday House
Six Hills Way, Stevenage
Herts, SG1 2AY, United Kingdom
www.theiet.org
While the authors and publisher believe that the information and guidance given in this work are correct, all parties must rely upon their own skill and judgement when making use of them. Neither the authors nor publisher assumes any liability to anyone for any loss or damage caused by any error or omission in the work, whether such an error or omission is the result of negligence or any other cause. Any and all such liability is disclaimed.
The moral rights of the authors to be identified as authors of this work have been asserted by them in accordance with the Copyright, Designs and Patents Act 1988.
British Library Cataloguing in Publication Data
A catalogue record for this product is available from the British Library
ISBN 978-1-83953-081-4 (hardback)
ISBN 978-1-83953-082-1 (PDF)
Typeset in India by MPS Limited
Printed in the UK by CPI Group (UK) Ltd, Croydon
| ANN | artificial neural network |
| BCNN | binary convolutional neural network |
| BNN | bitwise neural network |
| CNN | convolutional neural network |
| DNN | deep neural network |
| DRAM | dynamic random-access memory |
| FPGA | field programmable gate array |
| HDD | hard disk drive |
| IMC | in-memory computing |
| ML | machine learning |
| NDC | near-data computing |
| NVM | nonvolatile memory |
| ODD | optical disk drive |
| PCM | phase change memory |
| PIM | processing-in-memory |
| ReRAM | resistive random-access memory |
| ResNet | residual network |
| SLFN | single-layer feedforward neural network |
| SRAM | static random-access memory |
| STDP | spike timing-dependent plasticity |
| STT-MTJ | spin transfer torque magnetic tunnel junction |
| STT-RAM | spin transfer torque RAM |
| TNN | tensor neural network |
| TSV | through-silicon via |
| XIMA | crossbar in-memory architecture |
| 1S1R | one selector one ReRAM |
| 1T1R | one transistor one ReRAM |
With the emergence of IoT and handheld devices, the amount of data procured in the data centers have reached nearly exa-scale. Processing such large amounts of data through traditional computing techniques is inefficient due to latency and inefficient resource usage. With the introduction in machine learning (ML) and success in multiple application, ML has been adopted for big data processing.
Despite advancements in terms of processing through ML, transferring and communicating the data to and from the memory and storage units is seen as one of the major bottlenecks. In-Memory Computing (IMC) is seen as a panacea to overcome the challenges of traditional Von-Neumann architectures. For efficient IMC, frameworks such as Hadoop and MapReduce frameworks have been introduced. Such frameworks explore the temporal locality to process such large amounts of data. Despite efficient compared to traditional computing paradigms, existing IMC paradigms are inefficient in terms of power consumption and latency requirements, especially when employed in data centers and other cloud computing platforms.
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