Weng Fook Lee - Learning from VLSI Design Experience

This Springer imprint is published by the registered company Springer Nature Switzerland AG

The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland

Digital systems are widely used in our daily lives. From household appliances to mobile smartphone and tablets, digital IC (integrated circuits) chips form a large part of our lives, whether we can clearly identify the presence of these IC chips in the systems we use. As technology becomes a bigger part of our lives, these IC chips increase in complexity from a few thousand transistors (Intels 4004 in 1971) to 3.3 billion transistors (Apples A10 Fusion in 2016). More and more functionalities are cramped into a single IC chip increasing its complexity. It is common to find IC chips with few million transistors and more. Such complexity increases the difficulty level for IC designers to design the circuitry for the IC chips. Digital design methodology and flow are used with Hardware Description Language such as Verilog to aid the designer to design these complex circuitries.

Chapter discusses about analog/custom design flow and digital design flow. Technical details on each step of the flow are discussed from RTL (Register-Transfer Level) coding through simulation, synthesis, auto place and route to final tapeout.

Chapter .

Clock tree synthesis which plays an important role in physical backend auto place and route is described in this chapter, describing how clock skew occurs between different clock paths. Floorplan of physical backend prior to clock tree synthesis is also discussed in Chap..

Chapter .

Differences between synchronous reset and asynchronous reset are also discussed in Chap. with examples of correct RTL coding for these reset conditions.

Latch inference is undesirable in logic design and should be avoided. Chapter discusses RTL coding conditions that lead to latch inference in a design. Examples of if-else statements and case statements that lead to latch inference are described in this chapter.

With majority of ASIC and SOC design being multimillion gates, testability of design becomes a critical issue. Chapter on handling multiple scan chains for large design.

For large design with multiple asynchronous clocks, Chap. also covers logic BIST and memory BIST and how it is used in ASIC and SOC.

Signed Verilog is important for design that requires computation for positive and negative, for example, field-oriented control logic for controlling of motor movements for complex motor such as Brushless Direct Current (BLDC) motor and Permanent Magnet Synchronous Motor (PMSM). Chapter discusses in detail the usage of signed and unsigned, with descriptions of the consequences of mixing signed and unsigned in the RTL.

State machines are commonly found in ASIC and SOC design. Chapter shows the different state machine encoding and RTL coding styles for designing state machine.

Blocking statements and non-blocking statements commonly found in procedural statements are also discussed in detail in Chap..

Chapter .

With todays complex large ASIC and SOC, it is important to ensure the RTL is well covered and verified with the testbenches. Code coverage is a method to measure the percentage of RTL code coverage by the corresponding testbenches. RTL code that are not exercised by the testbenches are identified by code coverage. Chapter also shows how designers can use the information obtained from code coverage reports to enhance the testbenches to cover the missing coverage.

All the chapters in this book consist of many pictures and diagrams to help the reader visualize and understand the design examples. Many examples are provided throughout the book to help assist the reader to understand the complications and issues presented and solutions to overcome them.

This books target audience are students learning VLSI design and young design engineers learning the art of VLSI design. This book explains design from a practical perspective based on years of design knowledge gained from experience.

Pyxis, Calibre, Kronos, Modelsim, Leonardo Spectrum, DFT Advisor, Fastscan, Testkompress, Logic BIST , MBISTArchitect, and HDL Designer are trademarks of Mentor Graphics Inc.

Composer is a trademark of Cadence Inc.

Cyclone and Aria are trademarks of Altera/Intel Corp.

This book would not have been possible without the help of many people. I would like to put forward a word of Thank You to my wife for her companionship; I am looking forward to many more years of companionship on this journey of life; to my kids, for sitting with me at the study table while I write this book and they work on their school assignments; and to my besties, LP, SC, and BH, thank you for your patience in listening to my endless stories and for always being there for me.