Volnei A. Pedroni - Circuit Design with VHDL

List of Fgures

Fundamental logic gates.

(a) Chain-type (linear delay) and (b) tree-type (log delay) structures for combinational processing arrays.

Multiplexer.

Address decoder.

Parity detector: (a) Chain-type (linear delay) and (b) tree-type (log delay) constructions.

A priority encoder: (a) Functional description; (b) Chain-type construction (linear delay); (c) Tree-type construction (log delay).

The need for binary-to-BCD conversion.

Division-based binary-to-BCD converter (a bad idea).

Double-dabble algorithm (illustrated using bin with N = 8 bits).

(a) Construction principle for the double-dabble algorithm (illustrated for bin with N = 9 bits); (b) numeric example, for N = 12 bits, with bin = 111111111111 ( = 4095).

BCD conversion when the signal to be converted is produced by a counter (a particular case).

FA unit: (a) Circuit ports; (b) Truth table; (c) Transistor-level implementation using CMOS logic.

(a) Addition operation and (b) carry-ripple adder.

Faster adders: (a) Dynamic carry-chain Manchester adder; (b) Carry-lookahead adder; (c) Kogge-Stone tree adder.

Adder arrays: (a) Chain type (linear delay) and (b) tree type (log delay).

Adder plus twos complementer, computing s = ab.

(a) Incrementer; (b) Decrementer; (c) Twos complementer.

Parallel multiplier.

Comparators of (a) equality and (b) greater-or-equal plus equality.

Arithmetic logic unit (ALU).

Carry, overflow, and new MSB in addition; (b) Cascaded adders.

(a) Equations for determining the carry-out bit, the overflow flag, and the sums new MSB in unsigned and signed addition; resulting (b) unsigned and (c) signed circuits.

Numeric examples for unsigned addition.

Numeric examples for signed addition.

Multiplication- and division-by-two by means of left or right shift, respectively, for (a) positive and (b) negative integers.

(a) Adder without overflow; (b) Adder with overflow and saturation.

IEEE 754-2008 standard representations for (a) 32- and (b) 64-bit FP numbers.

32-bit FP representations for (a) 5.0 and (b) 1.5.

Floating-point extension.

D-type latches (DLs): (a) Positive-level DL; (b) Negative-level DL; (c) Behavior of a positive-level DL, where the gray shades represent propagation delays.

Examples of DL constructions: (a) Ring of inverters (SRAM-like); (b) Ring of inverters with additional switch; (c) Detailed implementation based on (b).

D-type flip-flops (DFFs): (a) Positive-edge DFF; (b) Negative-edge DFF; (c) Behavior of a positive-edge DFF, where the gray shades represent propagation delays.

(a) Main time parameters of a DFF; (b) Metastability, which can occur when the forbidden time window is violated; (c) Most common synchronizer (also known as two-flop synchronizer).

Construction approaches for DFFs: (a) Master-slave DFF (employs two cascaded DLs of opposite levels); (b) Short-clock-based DFF (employs a single DL with a clock-narrowing circuit); (c) Example of a commercial implementation of the latter (by Intel).

DFFs with (a) enable and (b) clear (i.e., synchronous reset) capabilities.

T-type flip-flops (TFFs): (a) Basic implementation; (b) With toggle-enable capability. A TFF does not involve actual data.

(a) Glitchy and (b) glitch-free combinational outputs; (c) Helpful approach (register after combinational logic), which eliminates glitches and aligns the outputs to the system clock (ready also for clock-domain crossing).

Illustration of RTL abstraction (transfers between registers via combinational logic): (a) General principle; (b)(c) A practical example (finite state machine).

Shift registers: (a) Regular, operating as a serial-in/parallel-out circuit or as a delay line; (b) With data-loading capability, operating as a parallel-in/serial-out circuit.

Synchronous modulo-2 N counters using (a) the traditional serial-enable architecture and (b) the incrementer-based architecture.

Programmable synchronous counters of arbitrary modulo using (a) the traditional serial-enable architecture and (b) the incrementer-based architecture.

Asynchronous counter (each stage produces the clock for the next stage).

(a) Sequential, Gray, Johnson, and one-hot encodings for eight states; (b) Gray counter obtained from a regular counter followed by an XOR layer; (c) Johnson counter; (d) One-hot counter.

Signal generation examples.

Tapped delay line.

(a) Clock division by 6, 7, and 7/3; (b) Important features of the resulting signal.

Generic solution for frequency division by any integer with symmetric glitch-free output.

(a)(d) Clock dividers by even integers; (e)(f) A simple divider by even and odd integers.

Serial counters for a timer with BCD outputs: (a)(b) Each stage produces the clock for the subsequent stage (hence not completely synchronous); (c)(d) All stages are triggered by the same clock (completely synchronous). The former has skew accumulation (though this is fine in some applications) but slightly lower power consumption.

(a) PLL principle; (b) Internal details of the PFD, charge pump, and loop filter blocks.

Synchronization in clock-domain crossing: (a) Single bit, including also an unclocked case (two-flop synchronizer); (b) Data vector with control signal (mux-based synchronizer); (c) Data vector with request and acknowledge signals (handshake-based synchronizer); (d) Pointer transference (Gray-encoded synchronizer).

Frequency meter using Gray code to enter the main clock domain.

Frequency meter using a synchronizer to enter the main clock domain.

Reset alternatives: (a) DFF with conventional (asynchronous) reset; (b) With pseudo-synchronous application and removal; (c) With asynchronous application and truly synchronous removal.

(a) One of three clock-gating arrangements (check the others in the text) and (b) a corresponding timing diagram.

(a) One-shot circuit (reduces pulse length to a single clock period), here preceded by a synchronizer; (b) Pulse capturer (captures pulses that are even shorter than one-half of a clock period), which includes a synchronizer.