Slobodan Mijalković - A Practical Guide to Verilog-A: Mastering the Modeling Language for Analog Devices, Circuits, and Systems

A Practical Guide toVerilog-AMastering the ModelingLanguage for Analog Devices,Circuits, and SystemsSlobodan MijalkoviA Practical Guide to Verilog-A: Mastering the Modeling Language forAnalog Devices, Circuits, and Systems Slobodan Mijalkovi The Hague, Zuid-Holland, The Netherlands ISBN-13 (pbk): 978-1-4842-6350-1 ISBN-13 (electronic): 978-1-4842-6351-8 https://doi.org/10.1007/978-1-4842-6351-8 Copyright 2022 by Slobodan Mijalkovi This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. Trademarked names, logos, and images may appear in this book. Rather than use a trademark symbol with every occurrence of a trademarked name, logo, or image we use the names, logos, and images only in an editorial fashion and to the benefit of the trademark owner, with no intention of infringement of the trademark. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. While the advice and information in this book are believed to be true and accurate at the date of publication, neither the authors nor the editors nor the publisher can accept any legal responsibility for any errors or omissions that may be made.

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Printed on acid-free paper ToSilva and JonaTable of Contents About the Author xv About the Technical Reviewer xvii Acknowledgments xix Introduction xxi Chapter 1: Lexical Basis 1 Character Set and Tokens 1 Comments 3 Identifiers 4 Simple Identifiers 4 Escaped Identifiers 5 Hierarchical Names 6 Reserved Words 6 System Names 7 Compiler Directives 7 Numerical Literals 8 Integer Literals 8 Real Literals 11 String Literals 13 Operators 14 Punctuators 15 v Table of ConTenTs Chapter 2: Basic Types and Expressions 17 Basic Types 17 Integer Types 17 Real Types 18 String Types 19 Expressions 20 Primary Expressions 20 Arithmetic Expressions 22 Relational Expressions 23 Logical Expressions 24 Bitwise Expressions 25 Conditional Expressions 26 Concatenated Expressions 26 Expression Evaluation Order 28 Operator Precedence 28 Parenthesized Expressions 29 Short-Circuit Evaluation 30 Expression Containers 30 Assignment Patterns 30 Ranges 31 Chapter 3: Net-Discipline Types 33 Defining Signal Natures 33 Base Natures 34 Derived Natures 37 Predefined Natures 38 Defining Net-Discipline Types 41 Nature Binding Statements 41 Domain Binding Statements 43 vi Table of ConTenTs Nature Override Statements 43 Deriving Natures from Disciplines 44 Discipline Compatibility 44 Predefined Disciplines 46 Net Declarations47 Scalar Nets 47 Vector Nets 48 Ground Nets 49 Net Initialization 50 Accessing Net Attributes 51 Chapter 4: Modules and Ports 53 Defining Module Connectivity 53 Declaring Port Directions 54 Declaring Port Types 57 Connecting Modules by Instantiation 60 Explicit Port Mapping61 Positional Port Mapping63 Top-Level Instantiation and $root 64 Implicit Nets 66 Instantiation of SPICE Primitives 67 Chapter 5: Parameters 69 Parameter Declarations 69 Simple Parameters 70 Array Parameters 71 Permissible Value Ranges 72 Parameter Aliases75 Local Parameters 76 vii Table of ConTenTs Overriding Parameters 76 Instance Parameter Override 76 Hierarchical Parameter Override 80 Hierarchical System Parameters81 Chapter 6: Paramsets 85 Introducing Paramsets 85 Defining Paramsets 88 Paramset Parameters 88 Parameter Override Statements 90 Other Paramset Statements 92 Paramset Instantiation 92 Chapter 7: Procedural Programming 97 Variables 97 Simple Variables 98 Array Variables 99 Procedural Blocks 100 Analog Blocks 100 Block Procedural Statements 101 Assignment Statements 103 Scalar Assignments 104 Array Assignments105 Conditional Statements 106 if Statement 106 case Statement 108 Looping Statements 109 while Statement 110 viii Table of ConTenTs for Statement111 repeat Statement 112 Chapter 8: Branches 115 Declaring Branches 115 Scalar Branches 115 Vector Branches 117 Port Branches 119 Branch Signals 120 Signal Directions 120 Signal Access Functions 121 Unnamed Branches 123 Contributing Branch Signals 125 Direct Contribution Statements 125 Indirect Contribution Statements 127 Probe Branches 129 Value Retention 130 Switch Branches132 Chapter 9: Derivative and Integral Operators 135 Time Derivative Operator 135 Case Study: DC Motor 136 Time Integrator Operator 138 Case Study: Chemical Reaction System 139 Circular Integrator Operator 142 Case Study: Voltage-Controlled Oscillator 144 Indirect Contribution Equations 145 Case Study: Accelerometer 147 Probe Derivative Operator 149 ix Table of ConTenTs Chapter 10: Built-In Math Functions 153 Deterministic Functions 153 Logarithmic and Power Functions 154 Trigonometric Functions 155 Hyperbolic Functions 156 Limiting and Rounding Functions 157 Probabilistic Functions 158 Random Number Generation Function 158 Statistical Distribution Functions160 Chapter 11: User-Defined Functions 165 Defining Functions 165 Formal Arguments 166 A Return Variable 167 A Procedural Statement168 Calling Functions 170 Function References 170 Using Functions in Expressions 172 Function Called As Statements 172 Chapter 12: Lookup Tables 175 Table Data Structure 175 Jagged Array Grids 176 Preparing Table Data 178 Lookup Table Function 180 Input Variables and Data Source 181 Control String 183 x Table of ConTenTs Chapter 13: Small-Signal Functions 189 AC Analysis 190 AC Stimulus Function 190 Noise Analysis 192 White Noise Function 193 Flicker Noise Function 194 Look-Up Table Noise Functions 195 Correlated Noise Sources 199 Chapter 14: Filters 201 Time-Domain Filters 201 Absolute Delay Filter201 Transition Filter 202 Slew Filter 204 Frequency-Domain Filters 205 Laplace Transform Filters 206 The Z-Transform Filters 210 Chapter 15: Events 215 Event Control Statements 215 Global Event Functions 217 Monitored Event Functions 219 Cross Function 220 Above Function 224 Timer Function226 Chapter 16: Runtime Support 229 Elaboration Queries 229 Port Connections 229 Parameter Overrides230 xi Table of ConTenTs Simulation Queries 231 Analysis Type 231 Kernel Parameters 233 Dynamic Probing 236 Solver Support 238 Announcing Discontinuity 238 Bounding Time Step 241 Limiting Iteration Steps 242 Simulation Control 246 Announcing Severity 246 Terminating Simulation 247 Chapter 17: Input and Output 249 File Management 249 Opening Files 249 File Positioning 252 Error Status 254 Detecting End-of-File 254 Flushing Output 255 Closing Files 255 Reading Data 255 Reading a Line from a File 255 Reading Formatted Data 256 Displaying and Writing Data 259 Text Output 259 File Output 260 Writing Data to a String 262 Escape Sequences 263 xii Table of ConTenTs Chapter 18: Generative Programming 267 Generate Blocks 267 Generate Statements 269 Generate Regions 269 Conditional Generation 269 Looping Generation 272 Hierarchy Scope and Names 276 Order of Elaboration 278 Chapter 19: Attributes 281 Introducing Attributes 281 Attribute Assignments 281 Attribute Instances 283 Standard Attributes 286 Simulation Reports 286 Output Variables 288 Port Discipline Override 290 Chapter 20: Compiler Directives 293 File Inclusion 293 Macro Definition 295 Object-like Macros 295 Function-like Macros 296 Undefining Macros 298 Predefined Macros 299 Conditional Compilation 299 Default Transition Directive 302 xiii Table of ConTenTs Appendix 303 Reserved Words in Verilog-A 303 Keywords 303 Other Reserved Words 304 SPICE Compatibility 306 Index 309 xiv