Poornima Mrs.K - Principles Of CMOS VLSI Design A Full Detailed Text Book: CMOS VLSI Design : A Circuits And Systems

A Course Material on
VLSI Design
By
Mrs.K.Poornima
ASSISTANT PRO FESSOR
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
SASURIE COLLEGE OF ENGINEERING
VIJAYAMANGALAM 638 056
QUALITY CERTIFICATE

This is to certify that the e-course material Subject Code Subject
Class
: EC2354
: VLSI Design : III Year ECE

being prepared by me and it meets the knowledge requirement of the university curriculum.
Signature of the Author
K.POORNIMA ASSISTANT PROFESSOR
This is to certify that the course material being prepared by Mrs.K.Poornima is of adequate quality. She has referred more than five books among them minimum one is from aboard author.
Signature of HD
N.RAMKUMAR
ASSISTANT PROFESSOR
EC2354 VLSI DESIGN L T P C 3 0 0 3

AIM
To introduce the technology, design concepts and testing of Very Large Scale Integrated Circuits.

OBJECTIVES
To learn the basic CMOS circuits.
To learn the CMOS process technology.
To learn techniques of chip design using programmable devices.
To learn the concepts of designing VLSI subsystems.
To learn the concepts of modeling a digital system using Hardware Description Language.

UNIT I CMOS TECHNOLOGY 9 A brief History-MOS transistor, Ideal I-V characteristics, C-V characteristics, Non ideal I
V effects, DC transfer characteristics - CMOS technologies, Layout design Rules, CMOS process
enhancements, Technology related CAD issues, Manufacturing issues
UNIT II CIRCUIT CHARACTERIZATION AND SIMULATION 9 Delay estimation, Logical effort and Transistor sizing, Power dissipation, Interconnect,
Design margin, Reliability, ScalingSPICE tutorial, Device models, Device
characterization, Circuit characterization, Interconnect simulation
UNIT III COMBINATIONAL AND SEQUENTIAL CIRCUIT DESIGN 9 Circuit families Low power logic design comparison of circuit families Sequencing
static circuits, circuit design of latches and flip flops, Static sequencing element methodologysequencing dynamic circuits synchronizers
UNIT IV CMOS TESTING 9 Need for testing- Testers, Text fixtures and test programs- Logic verification- Silicon
debug principles- Manufacturing test Design for testability Boundary scan
UNIT V SPECIFICATION USING VERILOG HDL 9 Basic conceptsidentifiersgate primitives,
procedural assignments conditional statements,
switch level modeling, Design hierarchies, Behavioral
gate delays, operators, timing controls, Data flow and RTL, structural gate level and RTL modeling, Test benches, Structural gate level description of decoder, equality detector, comparator, priority encoder, half adder, full adder, Ripple carry adder, D latch and D flipflop.

TEXTBOOKS TOTAL = 45 ERIODS
1. Weste and Harris: CMOS VLSI DESIGN (Third edition) Pearson Education, 2005 2. Uyemura J.P: Introduction to VLSI circuits and systems, Wiley 2002.

REFERENCES
1. D.A Pucknell & K.Eshraghian Basic VLSI Design, Third edition, PHI, 2003
2. Wayne Wolf, Modern VLSI design, Pearson Education, 2003
3. M.J.S.Smith: Application specific integrated circuits, Pearson Education, 1997
4. J.Bhasker: Verilog HDL primer, BS publication,2001
5. Ciletti Advanced Digital Design with the Verilog HDL, Prentice Hall of India, 2003

S.No. Content Page No

UNIT I CMOS TECHNOLOGY
1.1 Prerequisites 1
1.2 A brief History 1
1.3 MOS transistor 2
1.4 Ideal I-V characteristics 3
1.5 C-V characteristics 3
1.6 Non ideal I- V effects 4
1.7 DC transfer characteristics 4
1.8 CMOS technologies 7
1.13 2 Marks with answer 21 UNIT II CIRCUIT CHARACTERIZATION AND SIMULATION
2.1 Prerequisites 25
2.2 Delay estimation 25
2.3 Logical effort 26
2.4 Transistor sizing 28
2.5 Power dissipation 28
2.6 Interconnect 32
2.7 Design margin 32
2.8 Reliability 33
2.9 Scaling 34 2.10 SPICE tutorial, Device models 36 2.11 Device & Circuit characterization 44 2.13 2 Marks with answer 52 UNIT III COMBINATIONAL AND SEQUENTIAL CIRCUIT DESIGN
3.1 Prerequisites 56
3.2 Circuit families 56
3.3 Low power logic design 60
3.4 Comparison of circuit families 60
3.5 Sequencing static circuits 60
3.6 Circuit design of latches and flip flops 61
3.7 Static sequencing element 67
3.8 Sequencing dynamic circuits 67
3.9 Synchronizers 68 3.10 2 Marks with answer 69

UNIT IV CMOS TESTING
4.1 Prerequisites 73
4.2 Need for testing 73
4.3 Testers, Text fixtures and test 74programs

4.5 Silicon debug principle 81
4.7 Design for testability 82
4.9 2 Marks with answer 86
UNIT V SPECIFICATION USING VERILOG HDL
5.1 Prerequisites 91
5.2 Basic concepts 91
5.3 Identifiers 94
5.4 Gate primitives 95
5.5 Gate delays 98
5.6 Operators 99
5.7 Timing controls 101
5.8 Procedural assignments conditional 103statements

5.9 Data flow and RTL 105
5.11 Behavioral and RTL modeling, Test 111benches

5.12 Structural gate level description of 117decoder

5.13 Equality detector 118
5.14 Comparator, priority encoder 118
5.15 Half adder, full adder, Ripple carry 120adder, D latch and D flip flop.

5.16 2 Marks with answer 123
5.17 University Question 127
5.18 Important Question and Answer 135

UNIT I
CMOS TECHNOLOGY PREREQUISITES
An MOS (Metal-Oxide-Silicon) structure is created by superimposing several layers of conducting, insulating, and transistor forming materials.
After a series of processing steps, a typical structure might consists of levels called diffusion, polysilicon, and metal that are separated by insulating layers. CMOS technology provides two types of transistors, an n-type transistor (n MOS) and a p-type transistor (p MOS).

These are fabricated in silicon by using either negatively doped silicon that is rich in electrons (negatively charged) or positively doped silicon that is rich in holes (the dual of electrons and positively charged).

For the n-transistor, the structure consists of a section of p-type silicon separating two diffused areas of n-type silicon.
The area separating the n regions is capped with a sandwich consisting of an insulator and a conducting electrode called the GATE.
Similarly, for the p-transistor the structure consists of a section of n-type silicon separating two p-type diffused areas.
1.1 A BRIEF HISTORY

The p-transistor also has a gate electrode. The gate is a control input and it affects the flow of electrical current between the drain and source. The drain and source may be viewed as two switched terminals.

An MOS transistor is termed a majority-carrier device, in which the current in a conducting channel between the source and drain is modulated by a voltage applied to the gate.
In an n-type MOS transistor (i.e.,nMOS), the majority carriers are electrons.

A positive voltage applied on the gate with respect to the substrate enhances the number of electrons in the channel (region immediately under the gate) and hence increases the conductivity of the channel.

The operation of a p-type transistor is analogous to the nMOS transistor, with the exception that the majority carriers are holes and the voltages are negative with respect to the substrate.

The switching behavior of an MOS device is characterized by threshold voltage, Vt. This is defined as the voltage at which an MOS device begins to conduct.
For gate voltage less than a threshold value, the channel is cut-off, thus causing a very low drain- to-source current.

Those devices that are normally cut-off (i.e., non-conducting) with zero gate bias are further classed as enhancement mode devices, whereas those devices that conduct with zero gate bias are called depletion mode devices.