R. Jacob Baker - CMOS: Circuit Design, Layout, and Simulation; 3rd Edition (IEEE Press Series on Microelectronic Systems)

Contents

Square-Law Equations

For a triode-operating long-channel NMOS device

For a long-channel NMOS device operating in the saturation region:

On the border between saturation and triode:

V DS,sat = V GS V THN and the drain current is called I D,sat , see

For the PMOS device equations make the following substitutions in the equations listed above

V DS V SD , V GS V SG , and V THN V THP .

All of the voltages and currents in the PMOS and NMOS equations are positive. For example, for the PMOS device to conduct a drain current requires V SG > V THP . For the NMOS to conduct a drain current requires V GS > V THN .

CMOS

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Library of Congress Cataloging-in-Publication Data:

Baker, R. Jacob, 1964
CMOS: circuit design, layout, and simulation / Jake Baker. 3rd ed.
p. cm.

Summary: The third edition of CMOS: Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks, the BSIM model, data converter architectures, and much more. The 3rd edition completes the revised 2nd edition by adding one more chapter (chapter 30) at the end, which describes on implementing the data converter topologies discussed in Chapter 29. This additional, practical information should make the book even more useful as an academic text and companion for the working design engineer. Images, data presented throughout the book were updated, and more practical examples, problems are presented in this new edition to enhance the practicality of the bookProvided by publisher.

Summary: The third edition of CMOS: Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks, the BSIM model, data converter architectures, and much moreProvided by publisher.

ISBN 978-0-470-88132-3 (hardback)
1. Metal oxide semiconductors, ComplementaryDesign and construction. 2. Integrated circuitsDesign and construction. 3. Metal oxide semiconductor field-effect transistors. I. Title.
TK7871.99.M44B35 2010
621.39732dc22 2010016630

To my wife Julie

Preface

CMOS (complementary metal oxide semiconductor) technology continues to be the dominant technology for fabricating integrated circuits (ICs or chips). This dominance will likely continue for the next 25 years and perhaps even longer. Why? CMOS technology is reliable, manufacturable, low power, low cost, and, perhaps most importantly, scalable. The fact that silicon integrated circuit technology is scalable was observed and described in 1965 by Intel founder Gordon Moore. His observations are now referred to as Moores law and state that the number of devices on a chip will double every 18 to 24 months. While originally not specific to CMOS, Moores law has been fulfilled over the years by scaling down the feature size in CMOS technology. Whereas the gate lengths of early CMOS transistors were in the micrometer range (long-channel devices) the feature sizes of current CMOS devices are in the nanometer range (short-channel devices).

To encompass both the long- and short-channel CMOS technologies in this book, a two-path approach to custom CMOS integrated circuit design is adopted. Design techniques are developed for both and then compared. This comparison gives readers deep insight into the circuit design process. While the square-law equations used to describe MOSFET operation that students learn in an introductory course in microelectronics can be used for analog design in a long-channel CMOS process they are not useful when designing in short-channel, or nanometer, CMOS technology. The behavior of the devices in a nanometer CMOS process is quite complex. Simple equations to describe the devices behavior are not possible. Rather electrical plots are used to estimate biasing points and operating behavior. It is still useful, however, for the student to use mathematical rigor when learning circuit analysis and design and, hence, the reason for the two-path approach. Hand calculations can be performed using a long-channel CMOS technology with the results then used to describe how to design in a nano-CMOS process.