Nagrath - Electronics: Analog and Digital

Over the years, based on the readers response and feedback, both the author and the publisher felt the need to update the text and to bring out the second edition of the book including the recent developments in the subject.

In this edition, the chapters on digital electronics have been updated and enlarged, in particular. However, necessary improvements have been made in the analog part as well.

Chapter 1 on semiconductors, now in its second edition, includes Halls effect and some improvement in diode, rectifiers and the transfer characteristics of MOS devices now include a problem on graphical analysis.

In small-signal model of BJT, clarity has been brought in dc and ac . Hybrid- model has been elaborated. Stress has been laid on h -parameter model for completeness and also it has been compared with the - r model. Biasing stability has been examined for both types of transistors and self-bias potential divider bias is recommended. Further, explanation for CB configuration has been advanced leading to r e model. Another additional feature is the emitter coupled pair (differential pair), which builds the background for OPAMP.

Unique treatment of frequency response of small-signal amplifiers holds the competition.

Power amplifiers have been introduced with the added feature of Class D. Completeness and completion of oscillators can still not be matched by many others.

In operational Amplifiers (OPAMP), the gain of difference mode and common mode leading to CMRR is made simple and straightforward. All applicationslinear and nonlinear are treated in detail.

Improvements in digital part

Chapter 8 has been introduced with buffer, glitches and strobes.

• Digital pulse response of various gates gives a clear picture of gate outputs.
• Digital logic families is now complete.
• Hardware design of gates continues to be a strong feature.

Chapter 9 begins with number systemsdecimal, binary, octal and hexadecimal, their inter- conversions and arithmetic, Codesbinary and ASCII, use of 1-compliment, 2-compliment and subtraction by 2-compliment.

Boolean relations, sum of products (sop) and product-of-sums (pos) methods, Karnaugh maps simplification and Quine McCluskey method of simplification have been updated.

Adders and subtractorshalf adder (HA) and full adder (FA), Principle of addition and subtraction by XOR gates and additionsubtraction complete system, which takes 2-compliment if the answer is negative, have been explained. As per my knowledge, this is perhaps the only book which presents the complete system.

Other combinational circuits are covered including comparator, parity checkers, multiplexer, demultiplexers, coders, decoders. Programmables arrays (PLAs) have been included in the chapter.

New examples and problems have been added at appropriate places.

Chapter 10Sequential Circuits and Systems.

This is the most updated and enlarged chapter. Each topic presents truth tables, proof, symbol and waveforms. Wherever required, manufacturers number, pinout and logic diagram are given which is unique in presentation.

Each topic includes new examples and problems at the end.

Flip-Flops (FFs)

The topic begins with basic memory cell to store 1/0. It then goes on to SR flip flop (FF) and clocked SR FF circuits, types of trigger-level and pulse, preset and clear enteries, pulse triggering-clock serial, positive edge triggering (0 to 1) (PT) and negative edge triggering (1 to 0) (NT). The gate circuits for generating PT and NT are presented.

The circuits and truth tables of PT/NT triggered SR FF have been advanced. Waveforms of clock, SR and Q are shown.

Converting SR FF to JK FF circuit and truth table proof with their advantages are given. It is followed by Master-Slave JK FF circuit.

Converting SR and JK to D and T flip flops have been explained.

Excitation table for all flip-flops has been includedmostly useful in the circuits composed of FFs. The state synthesis table for converting SR to JK, FFs based on excitation table is presented.

Registers

The registers, which store and manipulate data, of all four typesSISO, SIPO, PIPO, PISOare operationally explained through one diagram with their applications. Bidirectional shift circuits are shown and commercially available registers are listed.

With the help of an example of parallel in-serial-out, TTL54/7465, 8 bits, operation of a register is explained supported with a separately drawn control diagram.

Counters

Both asynchronous and synchronous counters designs are presented through triggering truth tables and UP/DOWN counters. Advantage of synchronous counters have been clarified. Non-binary and BCD counters have been explained in detailMOD-3, MOD-6 = MOD-3 2, MOD-5 and MOD10 = MOD2 5; binary and biquinary counts.

Also, presettable synchronous counter have been introduced and ring counters and twisted ring counters have been included.

State diagrams

Moore and Mealy models, supported with several examples, are put forward to arrive at logic diagram through state models.

Memory

All aspects of memory organization are presented in detail with circuitry.

ROM (read only memory), shown to be nonvolatile, has been addressed. It can be bipolar. MOS and CMOS both types are programmable but MOS can be erased and reprogrammed. For large data, magnetic and optical memories the common feature now. These cannot be addressed but have to be read sequentially. All aspects and devices such as tape, hard disk and floppy are explained followed by ROM (electronic), using diodes BJT and MOS. These are shown to be nonvolatile.

Two dimensional (X, Y) addressing of a ROM is explained with diagrams which is faster and shown to need smaller number of NANDs Word and bit expansion is explained with examples.

These techniques are equally applicable to RAMs.

In Random Access Memory (RAM), it is shown that any memory cell can be read and written, but the memory is volatile. RAM organization is fully explained with the help of figurestwo dimensional addressing etc. Bipolar RAM, which can be static only, is presented through detailed diagram of one cell with all controls. Then follows the connection diagram of static NMOS RAM.