Khaled Salah Mohamed - Bluetooth 5.0 Modem Design for IoT Devices

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Among various beacon schemes, Bluetooth Low Energy (BLE) beacon is one of the most promising systems for enabling IoT. Bluetooth Low Energy (BLE) is widely used as a low-power communication protocol for short-range IoT sensors. As the BLE standard requires greatly relaxed specifications compared to the classic Bluetooth standard, the implementation of a low-power BLE transceiver with a simple structure is possible.

Bluetooth Low Energy (BLE) is considered as a short-range, energy-efficient, low-power, and low-cost radio technology for enabling IoT. Bluetooth is short-range wireless communication standard designed with an intention of replacing cables connecting portable and desktop devices and building wireless networks for such devices and enabling communication to be established between these devices up to maximum distance of 100 meters without obstacles. Bluetooth features robustness, low cost, low complexity, and low power; it uses the free industrial, scientific, and medical (ISM) frequency band (2.42.48 GHz).

The Bluetooth specification is an open specification that is governed by the Bluetooth Special Interest Group (SIG). The Bluetooth SIG is led by its five founding companies and four new member companies who were added in late 1999.

This book provides an introduction to Bluetooth technology, with a specific focus on developing a hardware architecture for its modem. The major concepts and techniques involved in Bluetooth technology are discussed, with special emphasis on hardware mapping. The book starts simply to allow the reader to quickly master the basic concepts before addressing the advanced features.

This book differs from the researches published up to date in that it presents Bluetooth transceiver architecture suitable for implementation in an FPGA. It examines several digital algorithms for modulation and demodulation of Bluetooth signals, locking on the carrier phase, and synchronizing the symbol. Many of these previously analog designs have been translated to the digital domain.

The existing literature does not study modem architectures to determine an effective implementation to handle the variation in bit rate due to different constellations while minimizing redundant hardware required to operate on multiple constellations in an FPGA. Literature is also deficient on synchronization techniques for multiple constellations and the implementation of these techniques in an FPGA.

Unlike ASICs, FPGAs are reconfigurable, that is, their internal structure is only partially fixed at fabrication, leaving to the application designer the wiring of the internal logic for the intended task. This can significantly shorten design and production, and thus time to market, for FPGA-based systems. Although FPGAs tend to be slower and consume more power than ASICs, FPGA re-configurability can benefit platform longevity (which is extremely important in an era of fast-changing wireless communications standards) by allowing design changes/upgrades even in systems already in operation. This flexibility can be effectively exploited for rapid prototyping of advanced communications signal processing.

The main design issues for Bluetooth transceivers are not only low cost and low power consumption, but also quality performance. Classical designs of the Bluetooth receiver utilize data-aided techniques to correct carrier frequency offsets and symbol timing errors. Such techniques offer low-cost and reasonable performance. Non-data-aided techniques offer an alternate higher-performance approach to correct the same problems, at the penalty of an increased hardware complexity and cost.

Another purpose of this book is to investigate the trade-off between cost and performance when a Bluetooth transceiver is designed using non-data-aided techniques for clock and timing recovery. The Bluetooth transceiver supports (GFSK, /4DQPSK, 8DPSK) modulation techniques and is able to achieve data rates of 1 Mbps, 2 Mbps, and 3 Mbps.

Our proposed Bluetooth transceiver design is encoded in the VHDL hardware description language and implemented successfully on Spartan 3 Xilinx FPGA. The performance of the transceiver is experimentally tested using the Xilinx FPGA-embedded ChipScope logic analyzer. Non-data-aided timing recovery improves the BER performance by as high as 3 dB at an area penalty of ~15% of the total design size. Verifications at worst-case frequency offset show an error rate performance of 103 at Eb/N0 of 15 dB for GFSK, 104 at Eb/N0 of 13.4 dB for /4DQPSK, and 104 at Eb/N0 of 20 dB for 8DPSK.