Chu - FPGA Prototyping by Systemverilog Examples

This edition first published 2018
2018 John Wiley & Sons, Inc.

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Library of Congress Cataloging-in-Publication Data

Names: Chu, Pong P., 1959-author.
Title: FPGA prototyping by systemVERILOG examples. Xilinx MicroBlaze MCS SoC Edition
/ by Pong P. Chu, Cleveland State University.
Description: Hoboken, NJ, USA : Wiley, 2018. | Includes bibliographical references and index. |
Identifiers: LCCN 2018005487 (print) | LCCN 2018006519 (ebook) | ISBN
9781119282693 (pdf) | ISBN 9781119282709 (epub) | ISBN 9781119282662
(cloth)
Subjects: LCSH: Field programmable gate arrays--Design and construction. |
Prototypes, Engineering. | VHDL (Computer hardware description language)
Classification: LCC TK7895.G36 (ebook) | LCC TK7895.G36 C4835 2018 (print) |
DDC 621.39/5--dc23
LC record available at https://lccn.loc.gov/2018005487

Cover image: Courtesy of Pong P. Chu
Cover design by Wiley

1. Chapter 1
2. Chapter 2
3. Chapter 3
4. Chapter 4
5. Chapter 6
6. Chapter 11
7. Chapter 12
8. Chapter 13
9. Chapter 18
10. Chapter 20
11. Chapter 21
12. Chapter 22
13. Chapter 23

1. Chapter 1
2. Chapter 2
3. Chapter 3
4. Chapter 4
5. Chapter 5
6. Chapter 6
7. Chapter 7
8. Chapter 8
9. Chapter 9
10. Chapter 10
11. Chapter 11
12. Chapter 12
13. Chapter 13
14. Chapter 14
15. Chapter 15
16. Chapter 16
17. Chapter 17
18. Chapter 18
19. Chapter 19
20. Chapter 20
21. Chapter 21
22. Chapter 22
23. Chapter 23
24. Chapter 24
25. Chapter 25
26. Appendix

To my mother, Chi-Te, my wife, Lee, and my daughter, Patricia

HDL (hardware description language) and FPGA (field-programmable gate array) devices allow designers to quickly develop and simulate a sophisticated digital circuit, realize it on a prototyping device, and verify operation of the physical implementation. As the capacity of FPGA devices continues to grow, a device can accommodate an SoC (system on a chip) design, which integrates a processor, memory modules, I/O peripherals, and custom hardware accelerators into a single chip. This book uses a learning by doing approach and illustrates the FPGA and HDL development and design process by a series of examples in the SoC context.

The examples start with simple gate-level circuits, progress gradually through the RT (register-transfer) level modules, and lead to a functional embedded system with custom I/O peripherals and hardware accelerators. A simple SoC framework, FPro (abbreviated from the book title F PGA Pro totyping), is introduced as a platform to integrate all the design examples together. An FPro system contains a Xilinx MicroBlaze MCS soft-core processor, a video subsystem, and the MMIO (memory-mapped I/O) subsystem that can incorporate custom I/O cores. Except for the processor, all components are designed and coded from scratch. All the hardware and software examples can be synthesized, compiled, and physically tested on the prototyping board.

Focus The primary focus of this book is on developing efficient and reliable digital systems and effectively using HDL as a tool to describe the intended hardware. The HDL language itself is not the main subject and its coverage is limited to a small synthesizable subset. The book uses about a dozen proven code templates to provide the skeletal structures of various types of circuits. These templates are general and can easily be integrated to construct a large, complex system. Although this approach limits the freedom of syntactic expression, it helps us steer our effort to develop an innovative and efficient hardware architecture.

After discussing the fundamentals in , the book illustrates more complicated and sophisticated designs in the SoC context. Along the way, readers will learn many system-level concepts, including the derivation of a soft-core processor and IP (intellectual property) core based system, the partition and integration of software and hardware, and the development of custom I/O peripherals and hardware accelerators.

Although the book is intended for beginning designers, the examples follow strict design guidelines and prepare readers for future endeavors. The coding and design practice is forward compatible, by which we mean the following:

• The same practice can be applied to large designs in the future.
• The same practice can aid other system development tasks, including simulation, timing analysis, verification, and testing.
• The same practice can be applied to ASIC technology and different types of FPGA devices.
• The code can be accepted by synthesis software from different vendors.

The intended audience is students in an advanced digital design course as well as practicing engineers who wish to learn FPGA-and HDL-based developments. Readers need to have a basic knowledge of digital systems, usually a required course in electrical engineering and computer engineering curricula, and a working knowledge of the C/C++ language. Prior exposure to computer architecture, embedded system, and operating system is not necessary but will be helpful.