Sheldon Tan - Long-Term Reliability of Nanometer VLSI Systems: Modeling, Analysis and Optimization

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The analysis and optimization of circuit reliability has become one of the most critical challenges for high-performance digital circuits. While the underlying phenomenabias temperature instability (BTI), hot-carrier injection (HCI), time-dependent dielectric breakdown (TDDB), and electromigration (EM)have been known for many years, our understanding of the underlying physics has greatly improved over the past decade or so. Initially, such investigations were largely confined to device reliability researchers, but as these phenomena have begun to rear their heads in commercial designs and conventional models have fallen short, the scope of this research has expanded. There has been a greater focus in the design community on determining the impact of device-level reliability on system performance, built upon physics-based models. This book provides an excellent overview of some recent research in the area of interconnect and device reliability. The authors are widely recognized as leading researchers in this area, with scores of high-quality publications in this area.

The first part of the book focuses on EM. This is a phenomenon that leads to circuit failures as voids are formed in interconnects. For many decades, EM modeling was based on empirical modeling techniques, and there is a growing realization that such models are limited today for interconnect systems with numerous branches, fabrication technologies based on copper that use barrier/capping layers that block the migration of metal atoms, and an environment where on-chip temperatures are an increasingly serious factor in accelerating EM. This book provides a detailed view into physics-based EM modeling, starting from Korhonens equation that models the kinetics associated with stress evolution with an interconnect due to the electron wind force and the opposing back-stress. This is followed by an exposition of more recent numerical methods applied to two-pin nets and multi-segment interconnect trees. Fast solution methods under both static and dynamic stresses, as well as methods for determining wire immortality, are presented, and the impact at the full-chip level is analyzed.

The second part focuses on device-level reliability degradation due to BTI, HCI, and TDDB and begins with first-principles approach to explaining modeling methods at the transistor level. Bridges are then built from the language of transistor-level modeling to that of digital circuit design, determining the impact of degradation on aging on circuit timing, from library characterization to circuit analysis. Finally, methods for assuring performance through circuit optimization and guard-banding are presented, focusing on both combinational and sequential elements at the circuit level and considerations at the microarchitecture/system level.

In summary, I commend this book as an excellent source for anyone interested in learning about aging effects in CMOS circuits. The topics addressed herein range from modeling techniques for elemental transistors and wires to circuit analysis and optimization and proceed all the way up to architectural considerations.

Reliability has become a more serious design challenge for current nanometer very large-scale integrated (VLSI) circuits especially as the technology has advanced into 7 nm. It was expected that the future chips would show sign of reliability-induced age much faster than the previous generations. Among many reliability effects, electromigration (EM) and bias temperature instability (BTI) reliability effects have become major design constraints. EM is a physical phenomenon of the oriented migration of metal (Cu) atoms due to the momentum exchange between atoms and the conducting electrons. It can cause wire resistance change and thus functional failure of the system. With aggressive technology scaling, EM sign-off is becoming more difficult than before using traditional EM analysis approaches. BTI is a long-term transistor degradation mechanism, which gradually degrades the voltage threshold of a transistor and by consequent the switching delay of the gate and further to that the circuit path delay. Therefore, the modeling and estimation of its effects on circuit performance degradation have become imperative. Moreover, the mitigation techniques for BTI are also becoming vital in order to ensure that circuits are robust over their lifetime.

Part I focuses on the recent development of new physics-based EM models, chip-scale assessment techniques, and system-level EM-induced dynamic reliability management for many important computing systems. First, we go through the basic EM physics and the partial differential equation (Korhonens equation) for describing stress evolution in a confined wire. Then, we introduce recently proposed physics-based three-phase EM model, which consists of void nucleation, void incubation, and growth phases. The new model is more consistent with measured wire resistance changes over time for copper damascene wires than the two-phase EM model. We further present a fast EM numerical analysis method, FastEM, based on the finite difference time domain (FDTD) and the Krylov subspace method. Furthermore, we also introduce a fast EM immortality check for a general multi-segment interconnects, which is the natural extension of Blechs limit for a single segment. Multi-segment interconnect-based analysis method is then discussed to account for the interdependency between the branches in a tree wire. We also present a new physics-based dynamic compact EM model, which, for the first time, can predict the transient EM recovery effect in a confined metal wire. The new EM recovery-aware model can be further exploited to significantly extend the chip lifetime. We further present a novel IR-drop-based full-chip EM assessment method to analyze the EM-induced degradation in the power grid networks. This method is further integrated with full-chip thermal and residual stress analysis techniques so that the impact of cross-layout temperature and residual stress distributions can be taken into account.